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Knowledge base

A wiki subspace to share information and links to for mutual share of the course related materials. All users logged into CourseWare are granted write access. The content and accuracy of the information posted, linked articles and videos are not guaranteed by the B4M35PAP course teaching team. If time permits, we will assist in ensuring that the information is correct, or we will add comments.

Official RISC-V tests

Official tests are available on GitHub - riscv-software-src/riscv-tests. These are self-tests, so they rely on some of the instructions of the processor. It is thus necessary to use other means to test at least the instructions these tests rely on. The tests will jump to code of macro RVTEST_FAIL when the test fails, and to code of macro RVTEST_PASS if it passed. See GitHub - riscv/riscv-test-env/p/riscv_test.h for inspiration. You might have to define pass and fail macros yourself to make testing if test passed/failed easier.

SystemVerilog: Accessing nested modules registers from tb

SystemVerilog allows to access not only inputs and outputs of a module, but even its internal wires or wires of internal modules in tb. For example, it's possible to print out registers of a processor when the tb is finished without putting them as output of the processor top level. I have the processor top level design instance name set to uut, and inside of it there is module register_file instantiated as register_file_inst.

To print out all registers to stdout, I may use:

for (int i = 1; i < 32; i++) begin
    $display("R%0d:%0d", i, uut.register_file_inst.gprs[i]);

Or to output it to a file:

$writememh("registers.mem", uut.register_file_inst.gprs);

courses/b4m35pap/knowbase/start.txt · Last modified: 2024/01/12 07:41 by bohacfr2