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Official RISC-V tests

Official tests are available on GitHub - riscv-software-src/riscv-tests. These are self-tests, so they rely on some of the instructions of the processor. It is thus necessary to use other means to test at least the instructions these tests rely on. The tests will jump to code of macro RVTEST_FAIL when the test fails, and to code of macro RVTEST_PASS if it passed. See GitHub - riscv/riscv-test-env/p/riscv_test.h for inspiration. You might have to define pass and fail macros yourself to make testing if test passed/failed easier.

SystemVerilog: Accessing nested modules registers from tb

SystemVerilog allows to access not only inputs and outputs of a module, but even its internal wires or wires of internal modules in tb. For example, it's possible to print out registers of a processor when the tb is finished without putting them as output of the processor top level. I have the processor top level design instance name set to uut, and inside of it there is module register_file instantiated as register_file_inst.

To print out all registers to stdout, I may use:

for (int i = 1; i < 32; i++) begin
    $display("R%0d:%0d", i, uut.register_file_inst.gprs[i]);
end

Or to output it to a file:

$writememh("registers.mem", uut.register_file_inst.gprs);

VHDL: Accessing nested entities registers from tb

Similarly to SystemVerilog, VHDL also allows access to nested signals, starting with VHDL-2008. This feature is called external names in VHDL. Let's take the same example as with SystemVerilog. VHDL needs to know the type of the signal in the external name, so this complicates things a little. It's usually easier to first make an alias that will refer to the signal with external name, although it is not strictly necessary. External names are specified inside of `« »`. It should be possible to refer to signals, constants and variables via external names. Inputs and outputs don't seem to be directly supported.

Due to VHDL's type restrictions, a common package has to be made with the array type for gprs array that will be used in both the testbench top file and in the design - to match the types used. Using two distinct array types of same lengths and item type and doesn't seem to work. The type could be

  type gprs_array is array (1 to 32) of std_logic_vector(31 downto 0);

print_registers: process is
  -- The path to the signal here is relative, assuming this is in toplevel testbench entity.
  -- For absolute path, you would prepend a dot to signal path.
  -- The top level entity has to be specified, use name of the entity,
  -- ie. '.tb_top.uut.register_file_inst.gprs' if your entity is called tb_top.
  alias gprs is << signal uut.register_file_int.gprs : gprs_array >>; 
begin
    -- After another process changes print_registers_sig to true, registers are printed.
    -- This could be done at the end of the testcase.
    wait until print_registers_sig;
    for i in gprs'low to gprs'high loop
        report "R" & to_string(i) & ":" & to_hstring(gprs(i));
    end loop;
end process print_registers;

It's possible to make aliases in architecture header as well.

architecture a1 of an_entity
  alias my_signal is << .tb_top.uut.somewhere.in.the.design.there.is.a_signal : std_logic >>;
begin
  my_signal <= force '1'; -- Note that force will make sure the value is forced over the old value driven by the design.
                          -- It is possible to release the signal by assigning release.
end architecture;

If you were trying mixed language simulation with Verilog and VHDL (that is probably only supported by proprietary, though freely accessible, tools like ModelSim), it is not possible to refer to Verilog signals using external names. It is fine if the path enters Verilog in the middle, though.

CPU and GPU Programming Frameworks

New ones

AdaptiveCpp - https://github.com/AdaptiveCpp/AdaptiveCpp

Running CPU Designs on FPGA Hardware

There has been more projects where initial design from our course has advanced into bigger project

RVapo by Damir Gruncl and Edurad Lavuš - Damir Gruncl's Master's Thesis and wholemotion control project for RTEMS, Linux with RISC-V coprocessor, LinuxDays 2023 presentation
Experimental super-scalar CPU by Tomáš Veselý

I have discussed and even partially inspired some related projects at ČVUT FIT as well

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