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Sample behavioral waveforms for design file "Sdram_RD_FIFO.v"

The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "Sdram_RD_FIFO.v". The design "Sdram_RD_FIFO.v" has a depth of 512 words of 16 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

Fig. 1 : Wave showing read and write operation.

The above waveform shows the behavior of the design under normal read and write conditions with aclr .

Fig. 2 : Wave showing FIFO full operation.

The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.