====== Knowledge base ======

A wiki subspace to share information and links to for mutual share of the course related materials. All users logged into CourseWare are granted write access. The content and accuracy of the information posted, linked articles and videos are not guaranteed by the B4M35PAP course teaching team. If time permits, we will assist in ensuring that the information is correct, or we will add comments.

  * [[https://www.youtube.com/playlist?list=PL85jopFZCnbMfMRR25ENcRkhhAUGwP5C5|Playlist of the RISC-V Summit 2023 videos]]
  * [[https://www.robertwinkler.com/projects/riscv_book/|RISC-V Assembly Programmming by Robert Winkler]]
  
===== Official RISC-V tests =====
Official tests are available on [[https://github.com/riscv-software-src/riscv-tests|GitHub - riscv-software-src/riscv-tests]]. These are self-tests, so they rely on some of the instructions of the processor. It is thus necessary to use other means to test at least the instructions these tests rely on. The tests will jump to code of macro ''RVTEST_FAIL'' when the test fails, and to code of macro ''RVTEST_PASS'' if it passed. See [[https://github.com/riscv/riscv-test-env/blob/master/p/riscv_test.h|GitHub - riscv/riscv-test-env/p/riscv_test.h]] for inspiration. You might have to define pass and fail macros yourself to make testing if test passed/failed easier.

The simple script [[https://gitlab.fel.cvut.cz/b4m35pap/stud-support/-/blob/master/riscv/riscv-isa-test/run_tests.sh|run_tests.sh]] to run tests on own processor with simple environment is available in subdirectory [[https://gitlab.fel.cvut.cz/b4m35pap/stud-support/-/tree/master/riscv/riscv-isa-test|riscv/riscv-isa-test]] of the [[https://gitlab.fel.cvut.cz/b4m35pap/stud-support/|https://gitlab.fel.cvut.cz/b4m35pap/stud-support/]] repository. ''RVTEST_PASS'' is defined to end by ''ebreak'' and store '0' in 'a0' register. The ''RVTEST_FAIL'' ends by ''ebreak'' but the ''a0'' is set to the failed test number multiplied by two and one is added.

===== SystemVerilog: Accessing nested modules registers from tb =====

SystemVerilog allows to access not only inputs and outputs of a module, but even its internal wires or wires of internal modules in tb.
For example, it's possible to print out registers of a processor when the tb is finished without putting them as output of the processor top level. I have the processor top level design instance name set to ''uut'', and inside of it there is module ''register_file'' instantiated as ''register_file_inst''.

To print out all registers to stdout, I may use:
<code verilog>
for (int i = 1; i < 32; i++) begin
    $display("R%0d:%0d", i, uut.register_file_inst.gprs[i]);
end
</code>

Or to output it to a file:
<code verilog>
$writememh("registers.mem", uut.register_file_inst.gprs);
</code>

===== VHDL: Accessing nested entities registers from tb =====

Similarly to SystemVerilog, VHDL also allows access to nested signals, starting with VHDL-2008. This feature is called external names in VHDL. Let's take the same example as with SystemVerilog. VHDL needs to know the type of the signal in the external name, so this complicates things a little. It's usually easier to first make an alias that will refer to the signal with external name, although it is not strictly necessary. External names are specified inside of `<< >>`. It should be possible to refer to signals, constants and variables via external names. Inputs and outputs don't seem to be directly supported.

<note warning>
Due to VHDL's type restrictions, a common package has to be made with the array type for gprs array that will be used in both the testbench top file and in the design - to match the types used. Using two distinct array types of same lengths and item type and doesn't seem to work. The type could be
<code vhdl>
  type gprs_array is array (1 to 32) of std_logic_vector(31 downto 0);
</code>
</note>

<code vhdl>
print_registers: process is
  -- The path to the signal here is relative, assuming this is in toplevel testbench entity.
  -- For absolute path, you would prepend a dot to signal path.
  -- The top level entity has to be specified, use name of the entity,
  -- ie. '.tb_top.uut.register_file_inst.gprs' if your entity is called tb_top.
  alias gprs is << signal uut.register_file_int.gprs : gprs_array >>; 
begin
    -- After another process changes print_registers_sig to true, registers are printed.
    -- This could be done at the end of the testcase.
    wait until print_registers_sig;
    for i in gprs'low to gprs'high loop
        report "R" & to_string(i) & ":" & to_hstring(gprs(i));
    end loop;
end process print_registers;
</code>

It's possible to make aliases in architecture header as well.
<code vhdl>
architecture a1 of an_entity
  alias my_signal is << .tb_top.uut.somewhere.in.the.design.there.is.a_signal : std_logic >>;
begin
  my_signal <= force '1'; -- Note that force will make sure the value is forced over the old value driven by the design.
                          -- It is possible to release the signal by assigning release.
end architecture;
</code>

<note tip>
If you were trying mixed language simulation with Verilog and VHDL (that is probably only supported by proprietary, though freely accessible, tools like ModelSim), it is not possible to refer to Verilog signals using external names. It is fine if the path enters Verilog in the middle, though.
</note>


===== CPU and GPU Programming Frameworks =====

New ones

  * AdaptiveCpp - https://github.com/AdaptiveCpp/AdaptiveCpp

===== Running CPU Designs on FPGA Hardware  =====

There has been more projects where initial design from our course has advanced into bigger project

  * RVapo by Damir Gruncl and Edurad Lavuš - [[https://dspace.cvut.cz/bitstream/handle/10467/114963/F3-DP-2024-Gruncl-Damir-samproj_v2-3.pdf|Damir Gruncl's Master's Thesis]] and whole[[https://gitlab.fel.cvut.cz/otrees/fpga/rvapo-apps|motion control project]] for RTEMS, Linux with RISC-V coprocessor, [[https://youtu.be/bgaACl6kfmU|LinuxDays 2023 presentation]]
  * Experimental super-scalar CPU by Tomáš Veselý

I have discussed and even partially inspired some related projects at ČVUT FIT as well

  * Jan Medek, [[https://dspace.cvut.cz/bitstream/handle/10467/123186/F8-DP-2025-Medek-Jan-thesis.pdf|Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support]] ([[https://github.com/medexs/nuttx/tree/ibex-demo-system-on-basys3-and-nexys-video|git with NuttX port]], [[https://github.com/medexs/ibex-demo-system/tree/read-spi-rx-data-support|Ibex RISC-V system on Digilent Basys 3 and Digilent Nexys Video]] 
  * Ondřej Golasowski, [[https://dspace.cvut.cz/bitstream/handle/10467/123187/F8-DP-2025-Golasowski-Ondrej-thesis.pdf|RISC-V open-source microarchitecture analysis and optimization]] ([[https://github.com/HoneyGol-Microsystems/vesp-beta|VESP-BETA single-cycle RV32IMZicsr]])

===== Interactive Virtual VHDL Development Boards  =====

  * [[https://ghdl.github.io/ghdl-cosim/vpi/examples/other.html|GHDL: Other co-simulation projects]]
  * [[https://www.chuckstechtalk.com/software/2021/12/27/interactive-vhdl-testbench.html|Chuck's Tech Talk: An Interactive VHDL Testbench Using GHDL, Python, and Cocotb]]
  * [[https://github.com/chuckb/ghdl-interactive-sim|GitHub: ghdl-interactive-sim]]
  * [[https://gitlab.ensta-bretagne.fr/bollenth/ghdl-vpi-virtual-board|Théotime BOLLENGIER: GHDL VPI virtual board]]
  * [[https://github.com/nickg/nvc|GitHub: NVC]]
    * [[https://www.nickg.me.uk/nvc/|Nick Gasson: NVC]]
    * [[https://www.nickg.me.uk/nvc/manual.html#VHPI|NVC: VHPI]]
  * [[https://www.cocotb.org/|cocotb]]
  * [[https://www.pygame.org/|pygame]]

===== More MCU/CPU/FPGA/Control and RTOS/Linux Projects by OTREES  =====

  * [[https://gitlab.fel.cvut.cz/otrees/org/-/wikis/knowbase|OTREES Knowledge Base]]
  * [[https://gitlab.fel.cvut.cz/otrees/org/-/wikis/theses-defend|Defended Theses]]