https://cw.fel.cvut.cz/b231/ 2026-05-05T09:54:20+0200 https://cw.fel.cvut.cz/b231/ https://cw.fel.cvut.cz/b231/lib/tpl/bulma-cw/images/favicon.ico text/html 2018-09-18T20:59:04+0200 Anonymous (anonymous@undisclosed.example.com) https://cw.fel.cvut.cz/b231/courses/b4m35pap/tutorials/02/start?rev=1537297144&do=diff 2. Seminar - Basic components Exercise 1. Describe in Verilog following components. (It is highly recomended to test each individual component and do not suppose it works as expected.) Exercise 2. Describe in Verilog a three-port 32-bit register file containing 32 registers (inputs: A1, A2, A3, WD3, WE3, clk; outputs: RD1, RD2). Register file has two read ports and one write port. The read ports take 5-bit address inputs, A1 and A2, each specifying one of $2^5 = 32$