B4M35PAP - Pokročilé architektury počítačů

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Rozvrh cvičení 2017

• KN:E-2

Ing. Pavel Píša, PhD.

Ing. Michal Štepanovský, PhD. - v běhu ZS 2017 neučí

Syllabus

1. Introduction
Control flow computers and Data flow computers (Data driven, Demand driven). Flynn’s taxonomy. Parallel processing. Amdahl’s and Gustavson’s law. Metrics.

2. From scalar processors to superscalar processors (basic organization of superscalar processor)
Static, dynamic and hybrid scheduling of the instruction flow

3. Superscalar techniques I – Register data flow
Register renaming (Tomasulo’s algorithm) and data speculation. Precise exception support.

4. Superscalar techniques II – Instruction flow, speculation
Prediction and Predictors, Branch misprediction recovery

5. Superscalar techniques III - Memory data flow; VLIW and EPIC
Load bypassing and Load forwarding. Load speculation.; Data parallelism, SIMD and vector instructions in ISA; Loop-unrolling and software pipelining.

6. Memory subsystem
Non-blocking cache, Victim cache, Virtual memory and cache

7. Multiprocessor systems and Memory coherence
Distributed memory systems (DMS) and Shared memory systems (SMS). Symmetric multiprocessor systems (SMP). Coherence in SMP 

8. Multiprocessor systems and Memory consistency
Rules for memory operations, Sequential consistency and other consistency models.

9. Parallel computing I – Data consistency on multiprocessor system
Parallel computing concepts, Programming issues, Parallel programming paradigms, Message Passing Interface (MPI) and Open Multi-Processing (OpenMP)

10. Parallel computing II
Synchronization

11. I/O subsytem
PCIe, HyperTransport, QuickPathInterconnect

12. MPP and clusters, interconnection networks
Static and dynamic interconnection networks

13. Architecture perspectives